View ADV7850_4445825.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

complete av front end data sheet ADV7850 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features main features 4-port hdmi xpressview receiver 170 mhz video and graphics digitizer complete 3d comb video decoder stereo audio codec high speed serial output (tmds) hdmi support 3d tv support audio return channel (arc) extended colorimetry, including sycc601, adobe rgb, adobe ycc 601, and xvycc extended gamut color 4:1 hdmi 297 mhz receiver fast switching of hdmi ports (xpressview) 3d tv video format support hdcp 1.4 support with internal hdcp keys adaptive hdmi equalizer full hdcp repeater support s/pdif interface for 4 single-mode arc outputs up to 36-bit deep color support complete hdmi audio support audio extraction available support for up to 16 vsis (including thx media director ? ) high speed serial output (tmds 297 mhz) full transmitter support including encryption can operate in a transceiver configuration audio insertion available video and graphics digitizer digitizes rgb graphics up to 1600 1200 at 60 hz (uxga) sd, ed, and hd tv support up to 1080p at 60 hz low refresh rates (24 hz/25 hz/30 hz) support for 720p/1080p 13-channel analog video input channels with 2 outputs 3d comb video decoder full ntsc/pal/secam color standards support adaptive 3d comb filter video decoder advanced time-base correction (tbc) with frame synchronization for sd formats complete scart support advanced vbi data slicer if compensation filters audio codec 24-bit, 48 khz stereo codec 5-channel stereo analog input mux with a stereo output general internal edid ram for hdmi and graphics dual stdi (standard identification) function support for dual input detection simultaneous analog processing and hdmi monitoring for fast input switching applications hdtvs, set-top boxes, av receivers, projectors, video matrix switchers functional block diagram figure 1. 07758-001 adc adc adc adc adc video input mux hdmi tx cvbs scart g cvbs 2/yc scart rgb + cvbs audio in mux audio l/r audio l/r audio l/r hp l/r graphics rgb cvbs yc ypbpr scart b scart r y/g pb/b pb/r hdmi i 2 s interface sdp cvbs 3d comb yc scart cp ypbpr 525p/625p 720p/1080i 1080p/ uxga rgb ddr2 sdram output mux hdmi 1 hdmi 2 i 2 s s/pdif dsd/dst hbr mclk sclk audio output mclk sclk s/pdif 36 5 4 5 4 5 tmds ddc tmds ddc hdmi 3 tmds ddc hdmi 4 tmds ddc 5v hdmi + vga 5v edid reg spi interface edid eprom arc arc ADV7850 hs/vs/de clk data hs/vs/de clk data dac deep color hdmi rx fast switch hdcp keys
ADV7850 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 electrical cha racteristics ............................................................. 5 power specifications .................................................................... 6 analog specifications ................................................................... 7 video specifications ..................................................................... 9 timing c haracteristics .............................................................. 10 timing diagrams ........................................................................ 11 absolute maximum ratings .......................................................... 13 package thermal performance ................................................. 13 esd caution ................................................................................ 13 pin configuratio n and function descriptions ........................... 14 power supply sequencing .............................................................. 24 power - up sequence ................................................................... 24 power - down sequence .............................................................. 24 power su pply requirements ...................................................... 24 functional overview ...................................................................... 25 hdmi receiver ........................................................................... 25 analog front end ....................................................................... 25 standard definition processor ................................................. 26 component processor ............................................................... 26 vbi data processor (vdp) ....................................................... 27 tmds output ............................................................................. 27 external memory requirements .............................................. 27 other features ............................................................................ 27 audio overview .............................................................................. 28 analog audio mux functionality .......................................... 28 audio codec functionality ....................................................... 28 register map architecture ............................................................ 29 ou tline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 5 /12 revision 0: initial version
data sheet ADV7850 rev. 0 | page 3 of 32 general description the ADV7850 is a high quality, single chip, multiformat video decoder graphics digitizer with an integrated 4:1 multiplexed hdmi ? receiver. this multiformat 3d comb filter decoder supports the conversion of pal, ntsc, and secam standards in the form of a composite or an s - video input signal into a hdmi output stream . scart and overlay functionality are enabled by the ability of the ADV7850 to process cvbs and standard definition rgb signals simultaneously. the ADV7850 contains one main component processor (cp) that processes yprpb and rgb component formats, including rgb graphics. the ADV7850 can operate in quad hdmi and analog input mode, thus allowing for fast switching between the analog video inputs and hdmi. the ADV7850 supports the decoding of a component rgb/ yprpb video signal into a hdmi output stream. the support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other smpte and hd standards. the ADV7850 supports graphics digitization. the ADV7850 is capable of digitizing rgb graphics signals from vga to uxga rates and converting them into an hdmi output stream. internal edid ram is available for one graphic s port. the ADV7850 incorporates a quad input hdmi - compatible receiver that supports all hdtv formats up to 3d 1080p 60 hz and 2160p 24 hz. the ADV7850 supports full hdcp de c ryption with internal key storage. the ADV7850 features hdcp authentication on all ports simultaneously. the feature allows fast switching between hdmi ports. sync measurements and status monitoring are also available for all hdmi p orts . each hdmi port has dedi - cated 5 v d etect and h ot p lug a ssert pins. the hdmi receiver also includes an integrated equalizer that ensures robust opera - tion of the interface with cable lengths up to 30 meters. the hdmi receiver has advanced audio functionality, such as a mute flag, that prevents audible extraneous noise in the audio output. in addition , the hdmi receiver incorporates internal edid support, which can be made available in full power, power - down, and power - off modes. an i nternal regulator supplies external edid memory from the hdmi 5 v signal in power - off mode . the ADV7850 incorporates xpressview? fast switching on all hdmi input ports. using the analog devices, inc., hardware - based hdcp engine that minimizes software overhead, xpressview technology allows fast switching between any two hdmi input ports in less than 1 second. the ADV7850 offers a flexible audio output port for the audio data decoded from the hdmi stream. hdmi audio formats, including super audio cd (sacd) via dsd , d st, and hbr are supported. the ADV7850 also features the single mode audio return channel (arc) feature. arc simplifies cabling by combining upstream audio capability in a conventional hdmi cable. the stereo audio adc converts analog audio inputs and provides the data to the back end via the hdmi interface. the stereo audio dac receives i 2 s data from the back end and converts it to analog audio output. the audio output is available as both high impedance and a driven output, which is suitable for driving headphones directly. fabricated in an advanced cmos process, the ADV7850 is provided in a 19 mm 19 mm, 425 - ball, csp_ bga, surface - mount, rohs - compliant package, and is specified over the ? 20 c to + 70c tempera ture range.
ADV7850 data sheet rev. 0 | page 4 of 32 detailed functional block diagram figure 2. detailed functional block diagram 07758-a002 adc0 clam p 12 adc1 clam p 12 adc2 clam p 12 adc3 clam p 12 (a) (b) (c) (d) (a) (b) (c) hdcp eeprom pll equal- izer equal- izer hdcp block sampler sampler hs/cs, vs/field control and data parameter extraction packet processor hdmi processor vbi decoder interrupt controller audio processor video output form atter ttx_spi int1 int2 active peak and hsync depth noise and calibr ation offset adder macrovision and cgms detection sync source and polarity detect component processor (cp) standard definition processor (sdp) 2d comb 3d comb tbc macrovision detection video_out_2 cvbs yc scart rgb yprpb rgb sync1 hs_in vs_in tri1 to tri8 scl sda ddca_sda/ddca_scl ddcb_sda/ddcb_scl rxa_c rxb_c rxa_0 rxa_1 rxa_2 equal- izer sampler rxc_0 rxc_1 rxc_2 equal- izer sampler rxd_0 rxd_1 rxd_2 rxb_0 rxb_1 rxb_2 13-channel input matrix analog front end sync processing and clock generation tri-level slicer gain contro l digital fine clam p program- mable delay rxd_5v/hpad rxc_5v/hpac rxb_5v/hpab rxa_5v/hpaa ddcc_sda/ddcc_scl ddcd_sda/ddcd_scl tx_c tx_0 tx_1 tx_2 rxc_c rxd_c sync2 hdmi tx pll serializer tmds drivers hdmi encoder 5-channel stereo input matrix audio_l/r_1 audio_l/r_2 audio_l/r_3 audio_l/r_4 audio_l/r_5 audio_l/r_out adc dac dac_l/r_out hp_l/r_out ac_sclk ac_lrclk ac_sdi video_out_1 sync3 audio return channel (single mode only) arc_a arc_b spdif_in arc_c arc_d ac_mclk audio output form atter ha_p0 ha_p1 ha_p2 ha_p3 ha_p4 ha_p5 ha_sclk ha_mclk spi_eprom (a) (b) (c) (d) +3.3v_eprom hpd ddc_sda ddc_scl vga_sda/vga_scl int3 programmable decimation filters ddr2 sdram interface standard autodection vertical peaking horizontal peaking cti and lti fastblank overlay control color control 5v detect, hpa controller and 5v regulator edid/ repeater controller i 2 c control interface packet/ infoframe memory spi interface vbi data formatter video data processor i 2 c readback i 2 s audio pll standard identification color space conversion fast switching block + hdmi decode + mux hdcp eeprom hdcp block
data sheet ADV7850 rev. 0 | page 5 of 32 specifications avdd = 1.8 v 5%, vdd to gnd = 1.8 v 5%, pvdd = 1.8 v 5%, tx_avdd = 1.8 v 5%, tx_pvdd = 1.8 v 5%, savdd = 1.8 v 5%, sdvdd = 1.8 v 5%, cvdd = 1.8 v 5%, dvddio = 3.3 v 5%, tx_vdd33 = 3.3 v 5%, tvdd = 3.3 v 5%, ac_avdd = 3.3 v 5%. t min to t max = ?2 0c to + 70c, unless otherwise noted. electrical character istics table 1. parameter symbol test conditions /comments min typ max unit static performance resolution (each adc) n 12 bits integral nonlinearity inl 27 mhz (at a 12 - bit level) ? 3.0 to +8.0 lsb 54 mhz (at a 12 - bit level) ? 3.0 to +8.0 lsb 74.25 mhz (at a 12 - bit level) ? 4.0 to +7.0 lsb 108 mhz (at a 11 - bit level) ? 3.5 to +8.0 lsb 170 mhz (at a 9 - bit level) ? 0.7 to +1 .8 lsb differential nonlinearity dnl 27 mhz (at a 12 - bit level) ? 0.7 to +0.8 lsb 54 mhz (at a 12 - bit level) ? 0.7 to +0.8 lsb 75 mhz (at a 12 - bit level) ? 0.7 to +0.8 lsb 108 mhz (at a 11 - bit level) ? 0.7 to +0.8 lsb 170 mhz (at a 9 - bit level) ? 0.6 to +0.5 lsb digital inputs input high voltage v ih xtaln and xtalp pins 1.2 v input low voltage v il xtaln and xtalp pins 0.4 v v ih other digital inputs 2 v v il other digital inputs 0.8 v input capacitance c in 10 pf hdmi tmds differential pin capacitance 0.3 pf digital inputs (5 v tolerant) 1 input high voltage v ih 3.0 v input low voltage v il 0.8 v input current i in ?82 +82 a digital outputs output high voltage v oh 2.4 v output low voltage v ol 0.4 v high impedance leakage current i leak ddc_scl, ddca_sda, ddcb_scl, d dcb_sda, ddcc_scl, ddcc_sda, d dcd_scl , ddcd_sda, vga_scl, vga_sda , spdif_in, shared_edid 30 a i leak rxa_5v, rxb_5v, rxc_5v, rxd_5v and vga_5v 20 a i leak all other digital pins 10 a output capacitance c out 20 pf 1 the following pins are 5 v tolerant: hs_in1/tri 7 , hs_in2/tri 5 , vs_in1/tri 8 , vs_in2/tri 6 , ddca_scl, ddca_sda, ddcb_scl, ddcb_sda , ddc c _scl, ddc c _sda, ddc d _scl , ddc d _sda, vga_scl, vga_sda, tx_ddc_scl, tx_ddc_sda, rxa_5v, rxb_5v, rxc_5v, rxd_5v , and vga_5v .
ADV7850 data sheet rev. 0 | page 6 of 32 power specifications table 2 . parameter symbol min typ max unit test conditions /comments power requirements digital core power supply vdd 1.75 1.8 1.85 v digital i/o power supply dvddio 3.14 3.3 3.46 v memory interface analog power supply savdd 1.71 1.8 1.89 v memory interface digital power supply sdvdd 1.71 1.8 1.89 v d pll power supply pvdd 1.71 1.8 1.89 v video analog power supply avdd 1.71 1.8 1.89 v terminator power supply tvdd 3.14 3.3 3.46 v comparator power supply cvdd 1.71 1.8 1.89 v audio b lock s upply ac_avdd 3.14 3.3 3.46 v hdmi tx analog power supply tx_avdd 1.71 1.8 1.89 v hdmi tx digital power supply tx_pvdd 1.71 1.8 1.89 v hdmi tx pll r egulator power supply tx_vdd33 3.14 3.3 3.46 v current consumption 1 , 2 , 3 digital core supply current i vdd 400 440 ma digital i/o supply current i dvddio 3 4 ma dpll supply current i pvdd 36 45 ma video analog supply current i avdd 270 290 ma memory interface analog power supply i savdd 4 5 ma memory interface digital power supply i sdvdd 15 18 ma comparator supply current i cvdd 300 350 ma audio block supply current i ac_avdd 80 84 ma hdmi tx analog supply current i tx_avdd 20 25 ma hdmi tx digital supply current i tx_pvdd 43 50 ma hdmi tx pll r egulator supply current i tx_vdd33 2 5 ma terminator supply current 4 i tvdd 80 85 ma one port connected 280 290 ma four ports connected power - down currents 5 i vdd 1 ma i dvddio 1. 5 ma i pvdd 0. 5 ma i avdd 0. 5 ma i savdd 0. 5 ma i sdvdd 0. 5 ma i tvdd 0. 5 ma i cvdd 0. 5 ma i ac_avdd 1 ma i tx_avdd 2.5 ma i tx_pvdd 0.5 ma i tx_vdd33 0.5 ma power - up time t pwrup 25 ms 1 all maximum current values are guaranteed by characterization to assist in power supply design. 2 typical current consumption values are recorded with nominal voltage supply levels, smpte bar video pattern , and at room temperature. 3 maximum current consumption values are recorded with maximum rated voltage supply levels, moirex video pattern , and at m aximum rated temperature . 4 termination power supply includes tvdd current consumed off chip. 5 power - down mode entered by setting the i 2 c bit power_down high.
data sheet ADV7850 rev. 0 | page 7 of 32 analog specification s table 3 . parameter test conditions /comments min typ max unit clamp circuitry 1 input impedance clamps switched off 10 m analog (ain1 to ain12) adc midscale (cml) 0.91 v adc full - scale level cml + 0.55 v adc zero - scale level cml ? 0.55 v adc dynamic range 1.1 v clamp level (when locked) component input, y signal cml ? 0.12 v component input, pr signal cml v component input, pb signal cml v pc rgb input (r, g, b signals) cml ? 0.12 v cvbs input cml ? 0.205 v scart rgb input (r, g, b signals) cml ? 0.205 v s- video input (y s ignal) cml ? 0.205 v s- video input (c s ignal) cml v large clamp source current sdp only 0.3 ma large clamp sink current sdp only 0.4 ma fine clamp source current sdp only 9 a fine clamp sink current sdp only 8 a audio adc section 2 number of channels s tereo pair 1 channel full - scale input level 50 a rms resolution 24 bits dynamic range (stereo channel) a- weighted ?60 dbfs with respect to full - scale analog input 90 db total harmonic distortion + noise (stereo channel) ?3 dbfs with respect to full - scale analog input ? 85 db gain mismatch left - and right - channel gain mismatch 0.2 db crosstalk (left to right, right to left) ? 90 db gain error input signal = 2.8 v rms ? 1.1 db power supply rejection 1 khz, 300 mv p - p signal at avdd ? 89 db audio adc digital decimator filter characteristics 2 at 48 khz, guaranteed by design pass band 22.5 khz pass - band ripple 0.0002 db stop band 26.5 khz stop - band attenuation 100 db group delay 1040 s audio dac section 2 number of auxiliary output channels s tereo pair 1 channel resolution 24 bits full - scale analog output 1 .0 v rms dynamic range a- weighted ?60 dbfs with respect to full - scale code input 93 db total harmonic distortion + noise ?3 dbfs with respect to full - scale code input ? 89 db
ADV7850 data sheet rev. 0 | page 8 of 32 parameter test conditions /comments min typ max unit crosstalk (left to right, right to left) ? 104 db interchannel gain mismatch left - and right - channel gain mismatch 0.1 db gain error 1 v rms output 0.525 db power supply rejection 1 khz, 300 mv p - p signal at avdd ? 101 db audio dac digital interpolation filter characteristics 2 at 48 khz, guaranteed by design pass band 21.769 khz pass - band ripple 0.01 db transition band 23.95 khz stop band 26.122 khz stop - band attenuation 75 db group delay 580 s headphone amplifier 2 measured at headphone output with 32 load number of channels s tereo pair 1 channel dynamic range a- weighted ?60 dbfs with respect to full - scale code input 92 db total harmonic distortion + noise ?3 dbfs with respect to full - scale code input ? 86 db interchannel gain mismatch 0.1 db power supply rejection 1 khz, 300 mv p - p signal at avdd ? 82 db analog audio mux 2 number of input c hannels stereo pair 5 channel number of output c hannels stereo pair 1 channel gain m ismatch b etween l eft and r ight c hannel s 5 % reference section absolute voltage v ref 1.5 v 1 specified for external clamp capacitor of 100 nf. 2 guaranteed by lab characterization.
data sheet ADV7850 rev. 0 | page 9 of 32 video specifications table 4. parameter symbol test conditions /comments min typ max unit nonlinear specifications 1 differential phase dp cvbs input (modulated five - step) 0.5 degrees differential gain dg cvbs input (modulated five - step) 0.6 % luma nonlinearity lnl cvbs input (modulated five - step) 0.9 % noise specifications 1 measured at 27 mhz llc snr unweighted luma ramp 59 db snr unweighted luma flat field 60 db analog front - end crosstalk 60 db lock time specifications (sdp) 2 horizontal lock range 5 % vertical lock range 40 70 hz subcarrier lock range f sc 0.8 khz color lock - in time 60 lines sync depth range 20 200 % color burst range 1 200 % vertical lock time 300 ms horizontal lock time 100 lines chroma specifications (sdp) 1 chroma amplitude error 0.9 % chroma phase error 0.3 degrees chroma luma intermodulation 0.6 % 1 guaranteed by lab characterization. 2 guaranteed by design.
ADV7850 data sheet rev. 0 | page 10 of 32 timing characteristics data, spi, and i 2 c timing characteristics table 5. parameter symbol test conditions/comments min typ max unit clock and crystal crystal frequency 27 mhz crystal frequency stability 50 ppm i 2 c port 1 see figure 3 scl frequency 400 khz scl minimum pulse width high t 1 600 ns scl minimum pulse width low t 2 1.3 s start condition hold time t 3 600 ns start condition setup time t 4 600 ns sda setup time t 5 100 ns scl and sda rise time t 6 1000 ns scl and sda fall time t 7 300 ns stop condition setup time t 8 0.6 s reset feature reset pulse width 5 ms hdmi audio i 2 s port, master mode see figure 4 ha_sclk mark-space ratio t 15 :t 16 45:55 45:55 % duty cycle lrclk 2 data transition time t 17 end of valid data to negative ha_sclk edge 2 ns lrclk 2 data transition time t 18 negative ha_sclk edge to start of valid data 2 ns i2sx 3 data transition time t 19 end of valid data to negative ha_sclk edge 2 ns i2sx 3 data transition time t 20 negative ha_sclk edge to start of valid data 2 ns audio codec master clock ac_mclk frequency range f mclk 4.096 24.576 mhz ac_mclk frequency f mclk 128 f s hz spi read and write operations 1 see figure 5, figure 7, and figure 8 sclk frequency 13.5 mhz master mode ttx_sclk falling edge to cs /ttx_mosi valid t 21 , t 22 3.0 4.1 ns ttx_miso setup time t 23 15.3 ns ttx_miso hold time t 24 2.1 ns slave mode cs falling edge to ttx_sclk rising edge t 25 , t 26 4.0 ns ttx_sclk falling edge to cs rising edge t 27 , t 28 4.0 ns ttx_mosi setup time t 29 1.8 ns ttx_mosi hold time t 30 2.7 ns ttx_sclk falling edge to cs /mosi valid t 31 , t 32 7.3 15.5 ns 1 guaranteed by design. 2 lrclk is a signal accessible via ha_ap5. 3 i2sx are signals accessible via ball ha_ap1 to ball ha_ap4.
data sheet ADV7850 rev. 0 | page 11 of 32 timing diagrams figure 3. i 2 c timing figure 4. hdmi audio i 2 s timing figure 5. spi master mode timing 07758-003 sda scl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 ha_sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 s mode msb msb ? 1 t 15 t 16 t 17 t 19 t 20 t 18 msb msb ? 1 lsb msb t 19 t 20 t 19 t 20 notes 1. the suffix x refers to the i 2 s output 0, 1, 2, 3. 2. lrclk is a signal accessible via ha_ap5 ball. 3. i2sx are signals accessible via ha_ap1 to ha_ap4 ball. 07758-004 07758-007 t 21 t 22 t 23 t 24 t tx_sclk ttx_mosi ttx_cs ttx_miso
ADV7850 data sheet rev. 0 | page 12 of 32 figure 6. spi master mode overview figure 7. spi slave mode timing figure 8. spi slave mode overview ttx_cs ttx_sclk ttx_mosi ttx_miso 232221...32107654321 765 4321076543210 0 instruction (0x0b) 24-bit address dummy byte data out 1 data out 2 07758-008 07758-009 t 29 t 31 t 32 t 30 t tx_sclk ttx_mosi ttx_cs ttx_miso 07758-010 ttx_sclk ttx_mosi ttx_miso ttx_sclk ttx_sclk ttx_sclk cs 1 1 0 0 cpcl 1 0 1 0 cpha 76543210 76543210 t 25 t 26 t 27 t 28 w/r device address dummy byte data out 0
data sheet ADV7850 rev. 0 | page 13 of 32 absolute maximum rat ings table 6. parameter rating avdd to gnd 2.2 v vdd to gnd 2.2 v pvdd to gnd 2.2 v tx_avdd to gnd 2.2 v tx_pvdd to gnd 2.2 v savdd to gnd 2.2 v sdvdd to gnd 2.2 v cvdd to gnd 2.2 v dvddio to gnd 4.0 v tvdd to gnd 4.0 v ac_avdd to gnd 4.0 v maximum difference across all 1.8 v supplies ?0.3 v to +0.3 v maximum difference across all 3.3 v supplies ?0.3 v to +0.3 v maximum difference between 3.3 v domain supplies and 1.8 v domain supplies ?0.3 v to +2.2 v digital inputs voltage to gnd ?0.3 v to dvddio + 0.3 v digital outputs voltage to gnd ?0.3 v to dvddio + 0.3 v 5 v tolerant digital inputs to gnd 1 5.5 v analog inputs to gnd ?0.3 v to avdd + 0.3 v ?0.3v to ac_avdd + 0.3 v xtaln and xtalp to gnd ?0.3 v to pvdd + 0.3 v maximum junction temperature (t j max ) 125c storage temperature range ?65c to +150c infrared reflow soldering (20 sec) 260c 1 the following inputs are 3.3 v inputs but are 5 v tolerant: hs_in1/tri7, hs_in2/tri5, vs_in1/tri8, vs_in2/tri6, ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, ddcc_scl, ddcc_sda, ddcd_scl , ddcd_sda, vga_scl, vga_sda, tx_ddc_scl, tx_ddc_sda, rxa_5v, rxb_5v, rxc_5v, rxd_5v and vga_5v . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect d evice reliability. package thermal perf ormance to reduce power consumption when using the ADV7850 , the user is advised to turn off unused sections of the part. due to pcb metal variation, and , therefore , vari ation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with th e ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction tempera - ture using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): ( ) total jt s j wtt += where: t s is the package surface temperature (c). jt = 0.7c/w for the 425 - ball csp_bga. w total = ( pvdd i pvdd ) + (0.4 tvdd i tvdd ) + ( cvdd i cvdd ) + ( avdd i avdd ) + ( vdd i vdd ) + ( dvddio i dvddio ) + ( tx _ avdd i tx_avdd ) + ( tx_pvdd i tx_pvdd ) + ( savdd i savdd ) + ( sdvdd i sdvdd ) + ( tx_vdd33 i tx_vdd33 ) + ( ac_avdd i ac_avdd ) where 0.4 reflects the 40% of tvdd power that is dissipated on the part itself. esd caution
ADV7850 data sheet rev. 0 | page 14 of 32 pin configuration and function descripti ons figure 9 . pin configuration 07758-011 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a gnd gnd gnd rxb_2+ rxb_1+ rxb_0+ rxb_c+ arc_b tvdd rxc_2+ rxc_1+ rxc_0+ rxc_c+ arc_c gnd rxd_2+ rxd_1+ rxd_0+ rxd_c+ arc_d gnd gnd gnd a b arc_a hpa_a gnd rxb_2? rxb_1? rxb_0? rxb_c? hpa_b tvdd rxc_2? rxc_1? rxc_0? rxc_c? hpa_c gnd rxd_2? rxd_1? rxd_0? rxd_c? hpa_d gnd acmuxo ut_r acmuxo ut_l b c rxa_c+ rxa_c? cvdd gnd gnd gnd gnd vdd_eep rom tvdd tvdd tvdd tvdd tvdd tvdd gnd tvdd tvdd tvdd tvdd gnd gnd acmuxin _1r acmuxin _1l c d rxa_0+ rxa_0? cvdd rxd_5v vga_5v ddca_ scl ddca_ sda ddcb_ scl ddcb_ sda ddcc_ scl ddcc_ sda ddcd_ scl ddcd_ sda vreg gnd vga_scl vga_sda tvdd ac_avdd ac_avdd ac_avdd acmuxin _2r acmuxin _2l d e rxa_1+ rxa_1? cvdd rxc_5v gnd gnd acmuxin _3r acmuxin _3l e f rxa_2+ rxa_2? cvdd rxb_5v pll_lf gnd acmuxin _4r acmuxin _4l f g tvdd tvdd tvdd tvdd gnd test1 cvdd cvdd cvdd cvdd cvdd cvdd cvdd gnd gnd ac_avdd gnd acmuxin _5r acmuxin _5l g h ep_miso ep_mosi spdif_in rxa_5v gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd filta vref_au dio h j ep_cs ep_sck shared_ edid reset gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ac_avdd gnd iset filtd j k gnd gnd dvddio dvddio vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ac_avdd ac_avdd ac_ dacout_ r ac_ dacout_ l k l ha_ap5 ha_sclk int1 sda vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ac_avdd ac_avdd hpout_r hpout_l l m ha_ap4 ha_ap3/ int3 int2 scl vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ac_avdd gnd gnd gnd m n ha_ap2 ha_ap1 ac_mclk ac_ lrclk vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd pvdd pvdd xtaln xtalp n p ha_ap0 ha_mclk out ac_sdi ac_sclk vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd p r ttx_ sclk ttx_ mosi ttx_ miso ttx_cs vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd refn refp r t dvddio dvddio gnd gnd vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd avdd avdd avdd avdd t u tx_avdd tx_avdd gnd tx_ddc_ scl vdd vdd vdd vdd vdd vdd vdd test2 gnd gnd gnd avin13 avin12 avin11 avin10 u v tx_2+ tx_2? gnd tx_ddc_ sda avdd avdd avdd avdd v w tx_1+ tx_1? gnd tx_hpd gnd avout2 avin9 avin8 w y tx_0+ tx_0? gnd gnd a7 a3 a10 ba0 cke gnd dq6 dq7 dq0 dq8 udqs sdvdd savdd tri1 tri2 gnd avout1 sync3 avin7 y aa tx_c+ tx_c? tx_ avdd gnd a9 a5 a1 ba1 we gnd dq4 dq5 dq2 dq11 udqsn sdvdd gnd hs_in1/ tri7 vs_in1/ tri8 gnd tri3 hs_in2/ tri5 vs_in2/ tri6 aa ab gnd tx_ pvdd tx_ plvdd sdvdd a11 a6 a2 cas ras vref sdvdd ldqsn dq3 dq10 dq12 dq14 gnd sync1 avin3 gnd sync2 avin6 tri4 ab ac gnd tx_ rterm tx_ vdd33 sdvdd a8 a4 a0 cs ckn ck sdvdd ldqs dq1 dq9 dq15 dq13 gnd avin1 avin2 gnd avin4 avin5 gnd ac 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
data sheet ADV7850 rev. 0 | page 15 of 32 table 7 . pin function descriptions pin no. mnemonic description a1 gnd ground . a2 gnd ground . a3 gnd ground . a4 rxb_2+ digital input channel 2 t rue of port b in the hdmi i nterface. a5 rxb_1+ digital input channel 1 t rue of port b in the hdmi i nterface. a6 rxb_0+ digital input channel 0 t rue of port b in the hdmi i nterface. a7 rxb_c+ digital input clock t rue of port b in the hdmi interface. a8 arc_b single -e nded audio return channel of port b in the hdmi i nterface. a9 tvdd hdmi termination s upply (3.3 v) . a10 rxc_2+ digital input channel 2 t rue of port c in the hdmi i nterface. a11 rxc_1+ digital input channel 1 t rue of port c in the hdmi i nterface. a12 rxc_0+ digital input channel 0 t rue of port c in the hdmi i nterface. a13 rxc_c+ digital input clock true of port c i n the hdmi i nterface. a14 arc_c single -e nded audio return channel of port c in the hdmi i nterface. a15 gnd ground . a16 rxd_2+ digital input channel 2 t rue of port d in the hdmi i nterface. a17 rxd_1+ digital input channe l 1 t rue of port d in the hdmi i nterface. a18 rxd_0+ digital input channe l 0 t rue of port d in the hdmi i nterface. a19 rxd_c+ digital input clock true of port d in the hdmi i nterface. a20 arc_d single -e nded audio return channel of port d in the hdmi i nterface. a21 gnd ground . a22 gnd ground . a23 gnd ground . b1 arc_a single -e nded audio return channel of port a in the hdmi i nterface. b2 hpa_a hot plug assert for port a. b3 gnd ground . b4 rxb_2 ? digital input channel 2 c o mplement of port b in the hdmi i nterface. b5 rxb_1 ? digital input channel 1 c o mplement of port b in the hdmi i nterface. b6 rxb_0 ? digital input channel 0 c o mplement of port b in the hdmi i nterface. b7 rxb_c ? digital input clock c o mplement of port b in the hdmi i nterface. b8 hpa_b hot plug assert for port b. b9 tvdd h dmi termination s upply (3.3 v) . b10 rxc_2 ? digital input channel 2 c omplement of port c in the hdmi i nterface. b11 rxc_1 ? digital input channel 1 c omplement of port c in the hdmi i nterface. b12 rxc_0 ? digital input channel 0 c omplement of port c in the hd mi i nterface. b13 rxc_c ? digital input clock c omplement of port c in the hdmi i nterface. b14 hpa_c hot plug assert for port c. b15 gnd ground . b16 rxd_2 ? digital input channel 2 c omplement of port d in the hdmi interface . b17 rxd_1 ? digital input channel 1 c omplement of port d in the hdmi interface . b18 rxd_0 ? digital input channel 0 c omplement of port d in the hdmi interface . b19 rxd_c ? digital input clock complement of port d in the hdmi i nterface. b20 hpa_d hot plug assert for port d. b21 gnd ground . b22 acmuxout_r audio codec mux output right channel . b23 acmuxout_l audio codec mux output left channel . c1 rxa_c+ digital input clock true of port a in the hdmi i nterface. c2 rxa_c ? digital input clock c o mplement of port a in the hdmi i nterface. c3 cvdd hdmi c omparator s upply (1.8 v) . c4 gnd ground . c5 gnd ground . c6 gnd ground .
ADV7850 data sheet rev. 0 | page 16 of 32 pin no. mnemonic description c7 gnd ground . c8 vdd_eeprom external edid eeprom power s upply . c9 tvdd hdmi t ermination s upply (3.3 v) . c10 tvdd hdmi termination s upply (3.3 v) . c11 tvdd hdmi termination supply (3.3 v) . c12 tvdd hdmi termination supply (3.3 v) . c13 tvdd hdmi termination supply (3.3 v) . c14 tvdd hdmi termination supply (3.3 v) . c15 gnd ground . c16 tvdd hdmi t ermination s upply (3.3 v) . c17 tvdd hdmi termination s upply (3.3 v) . c18 tvdd hdmi t erminati on s upply (3.3 v) . c19 tvdd hdmi termination s upply (3.3 v) . c20 gnd ground . c21 gnd ground . c22 acmuxin_1r audio codec mux input 1 right channel . c23 acmuxin_1l audio codec mux input 1 left channel . d1 rxa_0+ digital input channel 0 true of port a in the hdmi i nterface. d2 rxa_0 ? digital input channel 0 c omplement of port a in the hdmi i nterface. d3 cvdd hdmi c omparator s upply (1.8 v) . d4 rxd_5v 5 v d etect p in for port d in the hdmi i nterface. d5 vga_5v 5 v d etect i/o for vga c onnector . d6 ddca_scl serial c lock for ddc b us of port a. ddca_scl is 5 v tolerant. d7 ddca_sda serial d ata for ddc b us of port a. ddca_sda is 5 v tolerant. d8 ddcb_scl serial c lock p ort for ddc b us of port b. ddcb_scl is 5 v tolerant. d9 ddcb_sda serial d ata p ort for ddc b us of port b. ddcb_sda is 5 v tolerant. d10 ddcc_scl serial c lock p ort for ddc b us of port c. ddcc_scl is 5 v tolerant. d11 ddcc_sda serial d ata p ort for ddc b us of port c. ddcc_sda is 5 v tolerant. d12 ddcd_scl serial c lock p ort for ddc b us of port d. ddcd_scl is 5 v tolerant. d13 ddcd_sda serial d ata p ort for ddc b us of port d. ddcd_sda is 5 v tolerant. d14 vreg voltage r egulator o utput. must be decoupled to gnd via 1 f capacitor. d15 gnd ground . d16 vga_scl serial c lock for vga i nterface. vga_scl is 5 v tolerant. d17 vga_sda serial data for vga i nterface. vga_sda is 5 v tolerant. d18 tvdd hdmi termination supply (3.3 v) . d19 ac_avdd audio b lock s upply (3.3 v) . d20 ac_avdd audio b lock s upply (3.3 v) . d21 ac_avdd audio b lock s upply (3.3 v) . d22 acmuxin_2r audio codec mux input 2 right channel . d23 acmuxin_2l audio codec mux input 2 left channel . e1 rxa_1+ digital input channel 1 true of port a in the hdmi interface . e2 rxa_1 ? digital input channel 1 complement of port a in the hdmi interface . e3 cvdd hdmi c omparator s upply (1.8 v) . e4 rxc_5v 5 v detect pin for port c in the hdmi i nterface. e20 gnd ground . e21 gnd ground . e22 acmuxin_3r audio codec mux input 3 right channel . e23 acmuxin_3l audio codec mux input 3 left channel . f1 rxa_2+ digital input channel 2 t rue of port a in the hdmi i nterface. f2 rxa_2 ? digital input channel 2 c omplement of port a in the hdmi i nterface. f3 cvdd hdmi c omparator s upply (1.8 v) . f4 rxb_5v 5 v d etect pin for port b in the hdmi i nterface. f20 pll_lf loop filter ball for audio codec pll .
data sheet ADV7850 rev. 0 | page 17 of 32 pin no. mnemonic description f21 gnd ground . f22 acmuxin_4r audio codec mux input 4 right channel . f23 acmuxin_4l audio codec mux input 4 left channel . g1 tvdd hdmi t ermination s upply (3.3 v) . g2 tvdd hdmi t ermination s upply (3.3 v) . g3 tvdd hdmi termination s upply (3.3 v) . g4 tvdd hdmi t ermination s upply (3.3 v) . g7 gnd ground . g8 test1 test pin. d o not connect . g9 cvdd hdmi comparator s upply (1.8 v) . g10 cvdd hdmi comparator supply (1.8 v) . g11 cvdd hdmi comparator supply (1.8 v) . g12 cvdd hdmi comparator supply (1.8 v) . g13 cvdd hdmi comparator supply (1.8 v) . g14 cvdd hdmi comparator supply (1.8 v) . g15 cvdd hdmi comparator supply (1.8 v) . g16 gnd ground . g17 gnd ground . g20 ac_avdd audio b lock s upply (3.3 v) . g21 gnd ground . g22 acmuxin_5r audio codec mux input 5 right channel . g23 acmuxin_5l audio codec mux input 5 left channel . h1 ep_miso external edid eeprom i nterface . h2 ep_mosi external edid eeprom i nterface . h3 spdif_in s/pdif d igital a udio i nput for audio return channel (arc). h4 rxa_5v 5 v d etect p in for port a in the hdmi i nterface. h7 gnd ground . h8 gnd ground . h9 gnd ground . h10 gnd ground . h11 gnd ground . h12 gnd ground . h13 gnd ground . h14 gnd ground . h15 gnd ground . h16 gnd ground . h17 gnd ground . h20 gnd ground . h21 gnd ground . h22 f i lta audio codec adc f ilter c apacitor . h23 vref_audio audio codec b lock r eference v oltage c apacitor . j1 ep_ cs external edid eeprom i nterface . j2 ep_sck external edid eeprom i nterface . j3 shared_edid edid s election s ignal for hdmi port d . j4 reset chip reset. active low. minimum low time guarantee reset is 5 ms. j7 gnd ground . j8 gnd ground . j9 gnd ground . j10 gnd ground . j11 gnd ground . j12 gnd ground . j13 gnd ground . j14 gnd ground .
ADV7850 data sheet rev. 0 | page 18 of 32 pin no. mnemonic description j15 gnd ground . j16 gnd ground . j17 gnd ground . j20 ac_avdd audio b lock s upply (3.3 v) . j21 gnd ground . j22 iset audio codec adc c urrent s ettings . j23 f i ltd audio codec dac f ilter c apacitor . k1 gnd ground . k2 gnd ground . k3 dvddio i/o s upply (3.3 v) . k4 dvddio i/o s upply (3.3 v) . k7 vdd video digital s upply (1.8 v) . k8 gnd ground . k9 gnd ground . k10 gnd ground . k11 gnd ground . k12 gnd ground . k13 gnd ground . k14 gnd ground . k15 gnd ground . k16 gnd ground . k17 gnd ground . k20 ac_avdd audio block s upply (3.3 v) . k21 ac_avdd audio block s upply (3.3 v) . k22 ac_ dacout _r audio codec dac output right c hannel . k23 ac_ dacout _l audio codec dac output left c hannel l1 ha_ap5 hdmi audio p ort o utput . l2 ha_sclk hdmi audio p ort s erial c lock o utput. l3 int1 external interrupt 1. l4 sda i 2 c port serial data input/output . l7 vdd video digital s upply (1.8 v) . l8 gnd ground . l9 gnd ground . l10 gnd ground . l11 gnd ground . l12 gnd ground . l13 gnd ground . l14 gnd ground . l15 gnd ground . l16 gnd ground . l17 gnd ground . l20 ac_avdd audio b lock s upply (3.3 v) . l21 ac_avdd audio b lock s upply (3.3 v) . l22 hpout_r headphone o utput r ight c hannel . l23 hpout_l headphone output l eft c hannel . m1 ha_ap4 hdmi audio p ort o utput . m2 ha_ap3 /int3 hdmi audio p ort o utput / external interrupt 3. this pin can be configured as a ttl output interrupt pin for the vdp spi interface. m3 int2 external interrupt 2. m4 scl i 2 c port s erial clock i nput. m7 vdd video digital supply (1.8 v) . m8 gnd ground . m9 gnd ground .
data sheet ADV7850 rev. 0 | page 19 of 32 pin no. mnemonic description m10 gnd ground . m11 gnd ground . m12 gnd ground . m13 gnd ground . m14 gnd ground . m15 gnd ground . m16 gnd ground . m17 gnd ground . m20 ac_avdd audio b lock s upply (3.3 v) . m21 gnd ground . m22 gnd ground . m23 gnd ground . n1 ha_ap2 hdmi audio p ort o utput . n2 ha_ap1 hdmi audio p ort o utput . n3 ac_mclk audio codec/dac clock input . n4 ac_lrclk audio dac left/right clock input . n7 vdd video digital supply (1.8 v) . n8 gnd ground . n9 gnd ground . n10 gnd ground . n11 gnd ground . n12 gnd ground . n13 gnd ground . n14 gnd ground . n15 gnd ground . n16 gnd ground . n17 gnd ground . n20 pvdd dpll s upply (1.8 v) . n21 pvdd dpll s upply (1.8 v) . n22 x taln crystal o utput . n23 x talp crystal input or external clock i nput . p1 ha_ap0 hdmi audio p ort o utput . p2 ha_mclkout hdmi audio m aster c lock o utput . p3 ac_sdi audio dac data i nput . p4 ac_sclk audio dac sclk i nput . p7 vdd video digital s upply (1.8 v) . p8 gnd ground . p9 gnd ground . p10 gnd ground . p11 gnd ground p12 gnd ground p13 gnd ground p14 gnd ground p15 gnd ground p16 gnd ground p17 gnd ground p20 gnd ground p21 gnd ground p22 gnd ground p23 gnd ground r1 ttx_sclk vbi data i nterface . r2 ttx_mosi vbi data i nterface . r3 ttx_miso vbi data i nterface .
ADV7850 data sheet rev. 0 | page 20 of 32 pin no. mnemonic description r4 ttx_ cs vbi data i nterface . r7 vdd video digital s upply (1.8 v) . r8 gnd ground . r9 gnd ground . r10 gnd ground . r11 gnd ground . r12 gnd ground . r13 gnd ground . r14 gnd ground . r15 gnd ground . r16 gnd ground . r17 gnd ground . r20 gnd ground . r21 gnd ground . r22 refn negative analog v ideo r eference o utput . r23 refp positive analog v ideo r eference o utput . t1 dvddio i/o s upply (3.3 v) . t2 dvddio i/o s upply (3.3 v) . t3 gnd ground . t4 gnd ground . t7 vdd video digital s upply (1.8 v) . t8 gnd ground . t9 gnd ground . t10 gnd ground . t11 gnd ground . t12 gnd ground . t13 gnd ground . t14 gnd ground . t15 gnd ground . t16 gnd ground . t17 gnd ground . t20 avdd video analog s upply v oltage (1.8 v) . t21 avdd video analog s upply v oltage (1.8 v) . t22 avdd video analog supply v oltage (1.8 v) . t23 avdd video analog supply v oltage (1.8 v) . u1 tx_avdd hdmi tx analog supply (1.8 v) . u2 tx_avdd hdmi tx analog supply (1.8 v) . u3 gnd ground . u4 tx_ddc_scl serial clock for ddc bus of hdmi tx. tx_ddca_scl is 5 v tolerant. u7 vdd video digital s upply (1.8 v) . u8 vdd video digital s upply (1.8 v) . u9 vdd video digital s upply (1.8 v) . u10 vdd video digital s upply (1.8 v) . u11 vdd video digital s upply (1.8 v) . u12 vdd video digital s upply (1.8 v) . u13 vdd video digital s upply (1.8 v) . u14 test2 test pin. d o not connect . u15 gnd ground . u16 gnd ground . u17 gnd ground . u20 avin13 analog v ideo mux i nput c hannel . u21 avin12 analog video mux i nput c hannel . u22 avin11 analog video mux i nput c hannel .
data sheet ADV7850 rev. 0 | page 21 of 32 pin no. mnemonic description u23 avin10 analog v ideo m ux input c hannel . v1 tx_2+ digital output channel 2 t rue of the hdmi tx. v2 tx_2 ? digital output channel 2 c omplement of the hdmi tx. v3 gnd ground . v4 tx_ddc_sda serial d ata for ddc b us of hdmi tx. tx_ddca_sda is 5 v tolerant. v20 avdd video analog supply v oltage (1.8 v) . v21 avdd video analog supply v oltage (1.8 v) . v22 avdd video analog supply v oltage (1.8 v) . v23 avdd video analog supply v oltage (1.8 v) . w1 tx_1+ digital output channel 1 t rue of the hdmi tx. w2 tx_1 ? digital output channel 1 c omplement of the hdmi tx. w3 gnd ground . w4 tx_hpd hot plug detect s ignal of the hdmi tx. w20 gnd ground . w21 avout2 analog video mux o utput 2 . w22 avin9 analog video mux input c hannel . w23 avin8 analog video mux input c hannel . y1 tx_0+ digital output channel 0 t rue of the hdmi tx. y2 tx_0 ? digital output channel 0 c omplement of the hdmi tx. y3 gnd ground . y4 gnd ground . y5 a7 sdram address l ine . y6 a3 sdram address li ne . y7 a10 sdram address l ine . y8 ba0 sdram b lock a ddress s ignal . y9 cke sdram c lock e nable . y10 gnd ground . y11 dq6 sdram data l ine . y12 dq7 sdram data l ine . y13 dq0 sdram data l ine . y14 dq8 sdram data l ine . y15 udqs sdram u pper data strobe true s ignal . y16 sdvdd memory interface s upply . y17 savdd sdram interface s upply . y18 tri1 digital input c apable of s licing bil evel or tri l evel i nput from scart or d - connector. y19 tri2 digital input c apable of s licing bil evel or tri l evel i nput from scart or d - connector. y20 gnd ground . y21 avout1 analog video mux o utput 1 . y22 sync3 this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. y23 avin7 analog v ideo m ux input c hannel . aa1 tx_c+ digital output c lock t rue of the hdmi tx. aa2 tx_c ? digital output clock c omplement of the hdmi tx. aa3 tx_avdd hdmi tx analog supply (1.8 v) . aa4 gnd ground . aa5 a9 sdram address l ine . aa6 a5 sdram address l ine . aa7 a1 sdram address l ine . aa8 ba1 sdram block address s ignal . aa9 we sdram write enable s ignal . aa10 gnd ground . aa11 dq4 sdram data l ine . aa12 dq5 sdram data l ine . aa13 dq2 sdram data l ine .
ADV7850 data sheet rev. 0 | page 22 of 32 pin no. mnemonic description aa14 dq11 sdram data l ine . aa15 udqsn sdram upper data strobe compl e ment s ignal . aa16 sdvdd memory interface s upply . aa17 gnd ground . aa18 hs_in1/tri7 hs on graphics port /digital input capable of slicing bilevel or trilevel input from scart or d - connector. the hs input signal is used for 5 - wire timing mode. this ball can also be used as a trilevel/bilevel input on the scart or d - connector. aa19 vs_in1/tri8 vs on graphics port /digital input capable of slicing bilevel or trilevel input from scart or d - connec tor. the vs input signal is used for 5 - wire timing mode. this ball can also be used as a trilevel/bilevel input on the scart or d- connector. aa20 gnd ground . aa21 tri3 digital i nput c apable of s licing bil evel or t ri l evel i nput from scart or d - connector. aa22 hs_in2/tri5 hs on graphics port/digital input capable of slicing bilevel or trilevel input from scart or d - connector. the hs input signal is used for 5 - wire timing mode. this ball can also be used as a trilevel/bilevel input on the scart or d- connector. aa23 vs_in2/tri6 hs on graphics port/digital input capable of slicing bilevel or trilevel input from scart or d - connector. the vs input signal is used for 5 - wire timing mode. this ball can also be used as a trilevel/bilevel input on the scart or d- connector. ab1 gnd ground . ab2 tx_pvdd hdmi tx d igital s upply (1.8 v) . ab3 tx_plvdd hdmi tx pll d igital s upply (1.8 v). it is important to ensure that this supply pin has a clean voltage input. ab4 sdvdd memory interface s upply . ab5 a11 sdram a ddress l ine . ab6 a6 sdram address l ine . ab7 a2 sdram address l ine . ab8 cas sdram i nterface column address select command signal. one of four command signals to the external sdram. ab9 ras sdram i nterface row address select command signal. one of four command signals to the external sdram. ab10 vref termination reference voltage for memory interface . ab11 sdvdd memory interface s upply . ab12 ldqsn sdram lower data s trobe compl e ment s ignal . ab13 dq3 sdram data l ine . ab14 dq10 sdram data l ine . ab15 dq12 sdram data l ine . ab16 dq14 sdram data l ine . ab17 gnd ground . ab18 sync1 this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. ab19 avin3 analog video mux input channel . ab20 gnd ground . ab21 sync2 this is a synchronization on green or luma input (sog/soy) used in embedded synchronization mode. ab22 avin6 analog v ideo m ux input c hannel . ab23 tri4 digital input capable of slicing bi level or tri level input from scart or d - connector. ac1 gnd ground . ac2 tx_rterm this signal sets the internal termination resistance. a 500 resistor between this ball and gnd should be used. ac3 tx_vdd33 hdmi tx pll regulator supply input (3.3v). this pin is an internal voltage regulator input. ac4 sdvdd memory interface supply . ac5 a8 sdram address l ine . ac6 a4 sdram address l ine . ac7 a0 sdram address l ine . ac8 cs sdram i nterface chip select. sdram cs e nables and disables the command decoder on the ram. one of four command signals to the external sdram. ac9 ckn sdram i nterface differential clock compliment output. all address and control output signals to the ram should be sampled on the positive edge of ck and on the negative edge of ckn. ac10 ck sdram i nterface differential cloc k right output. all address and control output signals to the ram should be sampled on the positive edge of ck and on the negative edge of ckn.
data sheet ADV7850 rev. 0 | page 23 of 32 pin no. mnemonic description ac11 sdvdd memory interface s upply . ac12 ldqs sdram lower data strobe true s ignal . ac13 dq1 sdram data l ine . ac14 dq9 sdram data l ine . ac15 dq15 sdram data l ine . ac16 dq13 sdram data l ine . ac17 gnd ground . ac18 avin1 analog video mux i nput c hannel . ac19 avin2 analog v ideo m ux input c hannel . ac20 gnd ground . ac21 avin4 analog v ideo m ux input c hannel . ac22 avin5 analog video mux input c hannel . ac23 gnd ground .
ADV7850 data sheet rev. 0 | page 24 of 32 power supply sequencing power-up sequence the recommended power-up sequence of the ADV7850 is as follows: 1. 3.3 v supplies 2. 1.8 v supplies figure 10. recommended power-up sequence notes reset should be held low while the supplies are being powered up. ? 3.3 v supplies should be powered up first. ? 1.8 v supplies should be powered up last. the ADV7850 can alternatively be powered up by asserting all supplies simultaneously. in this case, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level as the supplies are being established. power-down sequence the ADV7850 supplies can be powered down simultaneously as long as the 3.3 v supply domain does not go below the 1.8 v supply domain. power supply requirements table 8 shows the current rating recommendations for power supply design. these values should be used when designing a power supply section to ensure that an adequate current can be supplied to the ADV7850 . table 8. current rating recommendation for power supply design parameter rating i dvdd 600 ma i cvdd 450 ma i tvdd 400 ma i avdd 350 ma i ac_avdd 150 ma i tx_pvdd 100 ma i pvdd 60 ma i tx_vdd33 50 ma i sdvdd 50 ma i tx_avdd 50 ma i dvddio 20 ma i savdd 20 ma 07758-012 3.3v supplies power-up power supply (v) 3.3v supplies 1.8v supplies 1.8v supplies power-up 3.3v 1.8v
data sheet ADV7850 rev. 0 | page 25 of 32 functional overview hdmi receiver the ADV7850 front end incorporates a 4:1 multiplexed hdmi receiver with xpressview fast switching technology and support for hdmi features including arc and 3d tv . building on the feature set of analog device s existing hdmi devices, the ADV7850 also offers support for all hdtv formats up to 3d 1080p at 60 hz and 2160p at 24 hz . xpressview fast switching technology, using the analog devices hardware - based hdcp engine that minimizes software overhead, allows switching betwee n any two input ports in less than 1 second. with the inclusion of hdcp 1. 4 , the ADV7850 can receive encrypted video content. the hdmi interface of the ADV7850 all ows for authentication of a video receiver, decryption of encoded data at the receiver, and renewal of that authentication during transmission, as specified by the hdcp 1. 4 protocol . repeater support is also offered by the ADV7850 . the ADV7850 supports the a udio r eturn c hannel feature. there is a dedicated s / pdif input on which audio can be received for retransmission on the hdmi input. wide ranges of 3d video formats are supported , including frame packing up to 3d 1080p at 60 hz and 2160p at 24 hz . the hdmi receiver incorporates active equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi ca bling, especially at longer lengths and higher frequencies. it is capable of equaliz - ing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest hdmi data rates. the hdmi receiver offers advanced audio functionality. it sup- ports multichannel i 2 s audio for up to eigh t channels. it also supports a six - dsd channel interface with each channel carry - ing an oversampled 1 - bit representation of the audio signal as delivered on sacd. the ADV7850 can also receive hbr audio packet streams and outputs them through the hbr interface in an s / pdif format conforming to the iec 60958 standard. the receiver contains an audio mute controller that can detect a variety of conditions that may res ult in audible extraneous noise in the audio output. on detection of these conditions, the audio signal can be mute d to prevent audio clicks or pops. hdmi receiver features include: ? 4:1 multiplexed hdmi receiver ? hdmi, arc , and 3d f ormat support, dvi 1.0 ? 2 97 mhz hdmi receiver ? integrated equalizer ? high - bandwidth digital content protection (hdcp 1. 4 ) on background ports ? internal hdcp keys ? 36- /30 - bit deep color support ? pcm, hbr, ds d, and ds t audio packet support ? repeater support ? internal e - edid ram ? hot p lug a ssert output pin for each hdmi port analog front end the ADV7850 analog front end comprises four 170 mhz, 12 - bit adcs that digitize the analog video signal before applying it to the standard definition process or (sdp) or component processor (cp). the front end also includes a 13- channel input mux that enables multiple video signals to be applied to the ADV7850 without the requirement of an external mux. current an d voltage clamp control loops ensure that any dc offsets are set properly for the video signal. the clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. the adcs are configured to run up to 4 oversampling mode when decoding composite , s- video , or scart inputs. for component 525i, 625i, 525p, and 625p sources , 4 oversampling is performed. higher frequency video standards can be 2 or 1 oversampled. oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal - to - noise ratio (snr). optional internal antialiasing filters with programmable bandwidth are positioned in front of each adc. these filters can be used to band -li mit video signals, removing spurious out - of - band noise. the a dv7850 can support the simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed with the output under the control of i 2 c registers. analog front - end features include: ? four 170 mhz, 12 - bit nsv adcs that enable 10 - bit (sd)/ 12- bit ( cp ) video decoding ? 13- channel analog input mux that enables multiple source connections without the requirement of an external mux ? four current and voltage clamp control loops that ensure any d c offsets are set properly for the video signal ? scart functionality and sd rgb overlay on cvbs controlled by fast blank input ? scart source switching detection through the tri1 to tri 8 input s ? four programmable antialiasing filters
ADV7850 data sheet rev. 0 | page 26 of 32 standard definition proc essor the sdp is capable of decoding a large selection of baseband video signals in composite , s- video , and 525i/625i component formats. the video standards supported by the sdp include pal, pal 60, pal m, pal n, pal nc, ntsc m/j, ntsc 4.43, and secam. the ADV7850 can automatically detect the video standard and process it accordingly. the sdp has a 3d temporal comb filter and a five - line adaptive 2d comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according t o the video standard and signal quality with no user intervention required. the sdp has an if filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner saw filter. the sdp has specific luminance and chrominance para meter controls for brightness, contrast, saturation, and hue. the ADV7850 implements a patented adaptive digital line length tracking (adllt?) algorithm to track varying video line lengths from sources such as a vcr. adllt enables the ADV7850 to track and decode poor quality video sources (such as vcrs) and noisy sources (such as tuner outputs, vcr players, and camcorders). frame tbc ensures stable clock synchroniza - tion between the decoder and the downstream devices. the sdp also contains both a luma transient improvement (lti) block and a chroma transient improvement (cti) block. these increase the edge rate on the luma and chroma transitions, resulting in a sharper video image. the sdp has a macrovision? detection circuit that allows type i, type ii, and type iii macrovision protection levels. the decoder is also fully robust to all macrovision signal inputs. sdp features include: ? advanced adaptive 3d comb (using the external ddr 2 memory) ? adaptive 2d five - line comb filters for ntsc and pal that give superior chrominance and luminance separation for composite video ? full automatic detection and autoswitching of all worldwide standards (pal, ntsc, and secam) ? automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range ? proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners ? if filter block that compensates for hi gh frequency luma attenuation due to tuner saw filter ? lti and cti ? vertical and horizontal programmable luma peaking filters ? 4 oversampling ( 54 mhz) for cvbs, and s - video modes ? free - run output mode that provides stable timing when no video input is present or video lock is lost ? internal color bar test pattern ? advanced tbc with frame synchronization, which ensures nominal clock and data for nonstandard input ? color controls that include hue, brightness, saturation, and contrast component processor the cp section of the ADV7850 is capable of decoding and digitizing a wide range of component video formats in any color space. component video standards supported by the cp include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, vga up to uxga at 60 hz, and many other standards. the any - to - any, 3 3 csc matrix is placed between the analog front end and the cp section. this enables ypbpr - to - rgb and rgb - to - ycbcr conversions. many other standards of color space c an be implemented using the color space converter. the cp section contains circuitry to enable the detection of macrovision encoded ypbpr signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. cp fe atures include: ? 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats are supported ? supports 720p at 24 hz /25 hz formats ? manual adjustments including gain (contrast) , offset (brightness), hue , and saturation ? support for analog component ypbpr and rgb video formats with embedded synchronization, composite synchronization , or separate hs and vs ? any - to - any, 3 3 csc matrix that supports ycbcr - to - rgb and rgb - to - ycbcr, fully programmable or preprogrammable configurations ? synchronization sourc e polarity detector (sspd) that determines the source and polarity of the synchronization signals that accompany the input video ? macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) ? free - run output mode that provides stab le timing when no video input is present or video lock is lost ? arbitrary pixel sampling support for nonstandard video sources ? 170 mhz conversion rate, which supports rgb input resolutions up to 1600 1200 at 60 hz ? automatic or manual clamp - and - gain contr ols for graphics modes ? 32 - phase adc dll that allows optimum pixel clock sampling ? automatic detection of synchronization source and polarity by sspd block ? standard identification enabled by stdi block ? rgb that can be color space converted to ycbcr and decima ted to a 4:2:2 format for video - centric back - end ic interfacing
data sheet ADV7850 rev. 0 | page 27 of 32 vbi data processor ( vdp) vbi extraction of teletext, cc, wss, cgms, pdc, utc, vps, gemstar, and vitc data is performed by the vbi d ata p rocessor of the ADV7850 at interlaced, progressive, and high definition scanning rates. the data extracted can be read back over the spi interface. tmds output the ADV7850 incorporates a 297 mhz tmds o utput. this interface is designed to connect to any internal ic with an hdmi or dvi i nput p ort . the digital video interface contains a n hdmi and a dvi 1.0- compatible transmitter , and supports all hdtv formats up to 3d 1080p at 60 hz and 2160p at 24 hz . t he ADV7850 transmitter fully supports programmable avi infoframes. with the inclusion o f h d c p, t h e ADV7850 transmitter allows the secure transmission of protected conten t as specified by the hdcp protocol . the ADV7850 transmitter also fully supports edid read operations . the ADV7850 tmds o utput supports the audio mode received from the hdm i receiver, that is, pcm , hbr, ds d, and ds t. external memory requ irements the ADV7850 requires an external sdram for 3d comb and frame tbc. the ADV7850 supports ddr2 memories. double data rate 2 (ddr2) the ADV7850 can use ddr 2 external memory to simultane - ously provide 3d comb and frame tbc operation. it requires a minimum memory of 128 m b with a speed grade of 200 mhz at cas latency (cl) 3. the recommended ddr2 memory compatible with the ADV7850 include the mt47h32m16hr - 25e:g from micron technology, inc. other features the ADV7850 has one i 2 c host port interface. the ADV7850 has two programmable interrupt request output pins , int1 and int2. it also features a number of low power modes and a full power - down mode . the ADV7850 contains an internal power regulator to accommodate power - off mode . in this mode , the ADV7850 is powered from the 5 v supply of the hdmi /vga cable connected to a source device or devices. in this mode, edid can be read over an hdmi / vga ddc link . the ADV7850 is provided in a 19 mm 19 mm, rohs - compliant csp_bga package and is specified over the ? 20 c to +70c temperature range . for more detailed product information about the ADV7850 , contact your local analog devices sales office .
ADV7850 data sheet rev. 0 | page 28 of 32 audio overview figure 11 . audio b lock the ADV7850 supports an audio codec comprising a stereo adc and a stereo dac. a 5:1 stereo mux is placed in front of th e adc input. the dac output is a vailable as a line level output and is passed through an internal headphone amplifier. t he integrated headphone amplifier eliminates the need for an external amplifier when driving headphones. analog audio mux fun ctionality the ADV7850 has five stereo analog audio inputs and one stereo analog output. any one of the stereo input s can be connected to the stereo adc, and any one of the inputs can be connected to the stereo output. in the case of the analog output , the ADV7850 also supports mono in - stereo out put . the i /o connectivity is shown in table 9 . table 9. a nalog a udio i nputs to adc and a nalog a udio o utputs c onnection c apability mux input mux o utput adc i nput left right left right 1 left ok ok ok n/a right ok ok n / a ok 2 left ok ok ok n/a right ok ok n/a ok 3 left ok ok ok n/a right ok ok n/a ok 4 left ok ok ok n/a right ok ok n/a ok 5 left ok ok ok n/a right ok ok n/a ok the ADV7850 is designed to use a combination of internal and external resistances. measured from the system audio input connector, the total nominal input impedance is 32.1 k? . all analog system audio inputs are designed to support 2.8 v rms audio input. figure 12 shows a high level overview of the implementation. the input level at the analog audio input pins on the ADV7850 is 880 mv rms . however, the ADV7850 incorporates a gain stage to restore the mux output level to 1.0 v rms. an external line driver is required to restore the audio output signals to the scart specification of 2.8 v rms . analog audio mu x output signals are inverted with respect to mux input signals. figure 12 . high level overview of analog audio input / output configuration a factory calibration is applied during final test to ensure that the gain through the mux circuit remains within 5%. c alibra - tion is also applied to the adc reference current to ensure that the code swing from the adc remains within 5% across the part for a given input. extern al impedances with a tolerance of 1% are required. audio codec function ality the ADV7850 a udio codec requires an external mclk. for mclk with a frequency of 6.144 mhz, 12.288 mhz , or 24.576 mhz , the adc and dac sample rate is 48 khz. if the mclk is reduced to 5.6448 mhz, 11.2896 mhz , or 22.5792 mhz , the adc and dac sample rate reduce s to 44.1 k hz. the bandwidth of the digital filter is sufficient so that 20 khz pass band is maintained in this mode. the 32 khz sampling is also possible but with pass - band reduction . the system controller must set an i 2 c control to select the correct mode of operation for the internal pll so that it always generates an internal mclk of 6.144 mhz. a fixed oversamp le rate of 128 is implemented. the word depth of both the adc and dac is 24 bits. the adc and dac have in dependent lrclk and sclk signals but use a common mclk. the adc supports i 2 s mode, providing lrclk, sclk , and i 2 s signals. these signals are sent to t he hdmi tx and embedded into the hdmi stream. the dac supports i 2 s mode. the lrclk, sclk , and data signals must be provided by the back - end soc and must be frequency locked with the mclk but can be phase independ - ent. t he output level is 1 v rms full scale. there is one stereo headphone amplifier output capable of driving 32 ? loads at 1 v rms. the h eadphone output incorporates circuitry to suppress pop/click sounds during power - on/off cycle. 07758-013 audio_l/r_1 audio_l/r_2 audio_l/r_3 audio_l/r_4 audio_l/r_5 audio_l/r_out adc dac dac_l/r_out hp_l/r_out ac_sclk ac_lrclk ac_sdi ac_mclk to hdmi tx block audio pll i 2 s 5-channel stereo input matrix 07758-014 ADV7850 2.8 v rms input 2.8 v rms input 2.8 v rms input 2.8 v rms input 2.8 v rms input mux output internal impedance 10.1k 10.1k 10.1k 10.1k external impedance 22k 22k 22k 22k 22k 10.1k adc mux
data sheet ADV7850 rev. 0 | page 29 of 32 register map archite cture the registers of the ADV7850 are controlled via a 2 - wire serial (i 2 c- compatible) interface. the ADV7850 has 1 7 maps . the io map and hdmi tx map has a static i 2 c address es . all other map addresses must be programmed . this ensures that no address clashes on the system. figure 13 shows the register map architecture. table 5. register map name default address programmable address location at which address can be programmed io map 0x40 not programmable not applicable hdmi tx map 0xb8 not programmable not applicable vdp map 0x00 programmable io map, register 0xfe cp map 0x00 programmable io map, register 0x fd hdmi rx map 0x00 programmable io map, register 0xfb hdmi rx edid map 0x00 programmable io map, register 0xfa ksv map 0x00 programmable io map, register 0xf9 afe map 0x00 programmable io map, register 0xf8 infoframe map 0x00 programmable io map, register 0xf5 sdp_io map 0x00 programmable io map, register 0x f2 sdp map 0x00 programmable io map, register 0xf1 hdmi tx edid map 0x00 programmable io map, register 0xf0 tx udp map 0x00 programmable io map, register 0xef vfe 0x00 programmable io map, register 0xec memory map 0x00 programmable io map, register 0xeb audio codec map 0x00 programmable io map, register 0xe7 tx test map 0x00 programmable io map, register 0xe3 figure 13 . register map architecture io map slave address: 0x40 hdmi tx map slave address: 0xb8 vdp map slave address: programmable cp map slave address: programmable hdmi rx map slave address: programmable afe map slave address: programmable infoframe map slave address: programmable sdp_io map slave address: programmable sdp map slave address: programmable hdmi tx edid map slave address: programmable tx udp map slave address: programmable vfe map slave address: programmable memory map slave address: programmable audio codec map slave address: programmable tx test map slave address: programmable hdmi rx edid map slave address: programmable ksv map slave address: programmable scl sda 07758-015
ADV7850 data sheet rev. 0 | page 30 of 32 outline dimensions figure 14. 425-ball chip scale package ball grid array [csp_bga] (bc-425-1) dimensions shown in millimeters ordering guide model 1 notes temperature range packag e description package option ADV7850kbcz-5 2, 3 ?20c to +70c 425-ball chip scale package ball grid array [csp_bga] bc-425-1 eval-ADV7850ebz 3 low cost, blackfin-based evaluation board with ADV7850 (with hdcp keys) eval-ADV7850eb1z 3 ADV7850 evaluation board with complete audio support (with hdcp keys) 1 z = rohs compliant part. 2 speed grade: 5 = 170 mhz. 3 this part is programmed with internal hdcp keys. customers must have hdcp adopter status (consult digital content protection, llc, for licensing requirements) to purchase any components with internal hdcp keys. a b c d e f g h j k l m n p r 1517 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17.60 bsc sq 16 19 21 18 20 23 22 t u v w y aa ab ac 0.65 nom 0.35 nom 1.50 1.36 1.21 1.11 1.01 0.91 compliant to jedec standards mo-275-ppab-2. 11-22-2011-a 0.50 0.45 0.40 19.20 19.00 sq 18.80 coplanarity 0.12 bottom view detail a top view 0.35 nom 0.30 min ball diameter seating plane a1 ball corner a1 ball corner detail a 0.80 bsc
data sheet ADV7850 rev. 0 | page 31 of 32 notes
ADV7850 data sheet rev. 0 | page 32 of 32 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07758-0- 5 /12(0)

▲Up To Search▲

Price & Availability of ADV7850

	To Download ADV7850 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .